MEASURING MATERIAL, DOPANT LOSS,FROM POST-IMPLANT WAGER CLEANS
Maintaining the integrity of ultrashallow junctions (USJs)
after exposure to an increasing
number of high-dose implant resist cleaning steps is critical
for logic device manufacturing
at the 45 nm node and beyond. Use of SiGe in the PMOS regions
adds an additional
material challenge. A new short loop method provides accurate
relative measurements of
amorphized silicon or SiGe loss caused by different types
of strip/clean processes...more
SEMICONDUCTOR INTERNATIONAL NOVEMBER 2008
DEFECT-FREE HIGH TEMPERATURE PROCESSING
innovations in RTP play a key role in SOI wafer production
for 45nm and beyond.Rapid Thermal Processing (RTP) was introduced
in silicon-on-insulator (SOI) wafer production for surface
smoothing to combine thickness control and surface quality
assurance.For sub-45nm technology node defect-free processing,
RTP is an important step in the production cycle, as specifications
become critical with respect to crystal defect reduction,
particularly on the backside of the wafer. Stringent lithography
requirements and yield concerns require total defect- and
stress-free processing.The temperature non-uniformity limit
over the 300-mm substrate, independent of bulk or SOI, approaches
3 to 5°C, while the maximum annealing temperature approaches
the melting point of silicon for improved surface smoothing
performances. These groundbreaking changes to meet future
technology requirements drive important innovations and at
the same time, present unique challenges for equipment manufacturers.One
of the new technologies introduced to RTP systems is a rotating
susceptor (wafer support) technology. This unique processing
feature is important for the wafer manufacturing industry.
The entire RTP system must not only precisely control the
process for SOI or bare silicon substrates, it must also be
reliable and repeatable at an acceptable cost per wafer for
a variety of customers in the silicon substrate manufacturing
arena, allowing the industry to keep on track with the ITRS
SUBSTRATE NEWS SUMMER 2008
50TH ANNIVERSARY PERSPECTIVES WORLDWIDE AND PERVASIE
EXPANSION OF SEMICONDUCTORS
On the occasion of Solid State Technology’s 50th anniversary,
the Solid State Technology's Editorial Advisory Board and
other luminaries to opine on the past 50 years and future
50 years of semiconductor manufacturing. We asked them a series
of questions: What were the key innovations that brought us
here? What major trends tell the most interesting story of
evolution and revolution? What new innovations will play a
significant role in semiconductor manufacturing-both in the
near-term and far-off future-and what new devices and technologies
might they enable? Their varied answers will surprise you.
Julie MacShane, Managing Editor ...More
STATE TECHNOLOGY NOVEMBER 2007
SELECTIVE OXIDATION OF ADVANCED GATE STACKS WITH TUNGSTEN
As a result of the reduction of critical MOSFET dimensions,
the conventional gate contact consisting of a stack of doped
poly-silicon and tungsten silicide is reaching its limits.
The replacement of the tungsten silicide by a tungsten/tungsten
nitride (W/WN) stack allows lower sheet resistances in combination
with smaller aspect ratios. In this stack, the WN interface
between poly-silicon and tungsten acts as a barrier against
silicidation during later thermal treatments. After deposition
and patterning of the gate stack, state-of–the-art complementary
metal oxide semiconductor (CMOS) circuits undergo rapid thermal
oxidation (RTO). During this process, the sidewall of the
stack is oxidized and damage caused by reactive ion etch (RIE)
and implantation is annealed in order to decrease gate and
gate-induced drain leakage. The differences in oxidation behaviour
of W/WN and tungsten silicide require the replacement of the
non-selective RTO process by a selective oxidation that only
oxidizes the silicon and not the tungsten metal. This selective
process oxidizes the lower poly-silicon sidewall while leaving
the W/WN sidewall unoxidized. The most appropriate approach
for such a selective process is a thermal oxidation in hydrogen-rich
steam. Thermodynamic considerations and experimental data
show that Si/SiO 2 and tungsten can coexist in a gas ambient
of up to approximately 20% H2O in H2 at temperatures which
are suitable for RTO (800°C – 1100°C).
MANUFACTURING Magazine China (English)
MANUFACTURING Magazine China (simplified Chinese)
October 24, 2006
MATTSON EXTENDS SELECTIVE OXIDATION TO ADVANCED GATE STACKS
Thermal budgets are becoming ever tighter, as memory manufacturers move beyond the 70nm node. Some manufacturers are also moving from batch furnaces to single-wafer tools to bypass the longer processing times arising from the larger thermal masses in conventional furnaces. With the introduction of its Atmos dual-chamber, single-wafer 300mm tool (based on its Helios platform), Mattson Technology Inc. says users will be able to address thermal budget constraints as they extend the well-known process of selective oxidation to more advanced nodes -- where material changes that accompany the smaller device geometries and thinner films mean structures are less forgiving with respect to over-processing.
Solid State Technology/WaferNews
October 1, 2006
THERMAL PROCESSING TAKES ON NEW MATERIALS, LOWER TEMPS
As new materials are introduced and smaller features required, thermal processing is evolving to meet the needs required by these factors, as well as hurdles imposed by smaller thermal budgets.
Of all the thermal oxides used in device manufacturing that must be precisely grown, doubtless the most critical of all these is gate oxide formation, which has become increasingly thinner from process node to process node. Over the years, gate oxide has gone from a thickness of ~250 Å in the late 1980s to 10 or fewer atomic layers, depending on the application.
Unlikely to slacken, this evolution will continue to require considerable R&D expenditures by device makers and equipment suppliers alike.
October 1, 2005
IS PORE SEALING KEY TO ULTRALOW-K ADOPTION?
One of the most straightforward ways to reduce RC delay, line-to-line capacitance and power consumption in devices is through the continual introduction of low-k dielectrics with decreasing k value (dielectric constant, k, or permittivity). One of the most likely paths involves incorporating low-k films with an increasing content of pores, or minute air bubbles on the order of angstroms to a few nanometers.
Semiconductor International, Technology Trends
August 1, 2005
EXTENDIBLE PROCESS USING UV-ENHANCED GATE DIELECTRIC
A SiON gate dielectric with 14.2 Å equivalent oxide thickness was formed using a novel UV-enhanced oxynitridation as the first step in a four-step gate stack process. The study demonstrates oxynitride's extendibility into the sub-18 Å EOT range with a leakage current density an order of magnitude lower than a conventional process.
Semiconductor International, Web Exclusive
LOW-TEMPERATURE RTP FOR SOURCE/DRAIN ENGINEERING
Relatively low-temperature rapid thermal processing offers some new alternatives for addressing the critical question of how to reduce source-drain parasitic resistance through ultralow thermal budget approaches. Solid-phase epitaxial regrowth and nickel silicide as a contact material are examined as potential solutions to reduce parasitic resistance with device scaling beyond the 65nm node.
Solid State Technology
May 14, 2005
UV-ENHANCED OXYNITRIDATION OF SILICON SUBSTRATES
The fundamental limit to the scaling of thin SiO 2 for ultra large scale integrated (ULSI) circuits is the large leakage current due to direct tunneling. Oxynitride films have been investigated as gate dielectrics due to their enhanced reliability relative to SiO 2 with comparable equivalent oxide thickness (EOT). In this paper we show the formation of an oxynitride layer on silicon using a novel UV-enhancement technique. The substrate is exposed to UV radiation in an ambient containing O 2 and N 2 . UV radiation is emitted from an external Xenon lamp with a broad wavelength (200-1100 nm) output. The photon energies from such Xenon lamp are 6.2 - 1.1 eV. We have used this UV-enhanced oxy-nitridation as the first step in a 4-step gate stack process, which is described below. The oxynitride thickness is about 6 Å based on an analysis of ellipsometric and electrical data of the final gate stack.
Semiconductor International China (simplified Chinese)
SEMICON China 2004 (English)
THERMAL BUDGET REDUCTION DRIVES RTP BEYOND THE 45NM NODE
Limits on thermal exposure are being driven by advanced node requirements and depend on the device's physical state at any given point, as well as the kinetics of the undesired phenomena that may arise from heat treatment (e.g., atomic diffusion, chemical reaction, defect formation, or phase changes). Rapid thermal processing (RTP) limits such negative side effects by minimizing thermal exposure, while providing a highly controlled ambient that eliminates contamination. Recent trends in RTP thermal budget reduction include “hotter and faster” processing that enables advanced ion-implant annealing processes for forming ultrashallow junctions (USJ), and the increasing use of RTP at relatively low process temperatures (<500°C) needed for advanced silicides.
Solid State Technology
USING AN ICP-BASED STRIP SYSTEM TO PERFORM RESIST AND
BARRIER-LAYER REMOVAL IN COPPER LOW-K PROCESSES
integration of copper interconnects and low-k dielectrics
in dual-damascene processes has been a
but difficult, step in the progress of IC technology. The
new materials used in interconnect layers are essential for
the higher-speed operations that
are required for advanced computing and communications applications.
Because copper is a better conductor than aluminum and the
materials is lower than that of silicon dioxide, copper/low-k
technology reduces resistance capacitance (RC)
delay for signals and accelerates the switching of logic
gates in the circuit.
RTP-GROWN OXYNITRIDE LAYERS MEET GATE CHALLENGES
RTP oxynitride layers grown in an NH3 ambient are found
to be very attractive gate dielectric candidates for
the 100 and 90 nm technology nodes, and may also
serve as an interfacial layer between the high-k gate dielectric and silicon
surface for 65 nm technology and below.
USJ FORMATION: ANNEALING BEYOND 90NM
The formation of ultrashallow junctions (USJ) poses major challenges as device
technology approaches the 65nm node. Three approaches for the formation of advanced
USJ structures are described and the sheet resistance (RS) and junction depth
(XJ) performance of the various techniques are compared.
Solid State Technology, Cover Story
USING A BIASED-ICP REACTOR FOR PR STRIP AND CU BARRIER
A 2-in-1 integration scheme — in which the barrier removal
and photoresist strip are done in situ following dielectric
etch — is proposed. Photoresist stripping and barrier
removal on SiLK, porous SiLK, and LKD-5109 dielectric materials
were evaluated with a process developed on blanket films and
later optimized on patterned wafers. Pattern wafer performance
was evaluated on single- and dual-damascene structures using
cross-section SEM and TEM.
Solid State Technology, Wafer Cleaning